Implementations of the present disclosure relate to a closed-loop, high-speed adaptive channel equalization for serial data communication.
Wireline serial communication systems are widely used for applications such as High-Definition Multimedia Interface (HDMI) systems, Digital Versatile Disc (DVD) players, and audio-visual (AV) systems. A major concern in such applications is the limited channel bandwidth, which causes inter-symbol interference and distortion for binary serial data such as no-return-to-zero (NRZ) and return-to-zero (RZ) sequences. This is further complicated by different cable lengths that may be used in different communication systems. Channel equalization is widely used in these serial communication systems to compensate for limited channel bandwidth as described by Sakano in U.S. Pub. No. 2010/0079216, filed Sep. 18, 2009, and incorporated by reference herein in its entirety. Channel equalization may be performed at the transmitter or the receiver or both in serial data communication systems. When performed at the transmitter, data is typically predistorted by amplifying the high frequency components of the data to compensate for the low-pass characteristic of the channel. When performed at the receiver, low frequency components of received data may be attenuated or high frequency components may be amplified by a channel equalizer to compensate for data distortion.
FIG. 1 is a typical serial data communication receiver as disclosed by Gerfers et al. in U.S. Pat. No. 8,396,105, filed Mar. 12, 2013, and incorporated by reference herein in its entirety. The circuit comprises an adaptable equalizer 10, a plurality of sampling amplifiers or samplers 12, a digital post-processing circuit 14, and a clock recovery circuit 16. A circuit input 11 receives serial data over a data channel and applies it to an input of equalizer 10, which has an output coupled to each of sampling amplifiers 12. Outputs from sampling amplifiers 12 are coupled to digital post-processing circuit 14. Digital post processing circuit 14 has one output coupled to a setting input of equalizer 10. Clock recovery circuit 16 has outputs coupled to sampling amplifiers 12. An input of clock recovery circuit 10 may be coupled to circuit input 11 or to a clock reference. FIG. 1B is an example of different equalizer 10 transfer characteristics. The transfer characteristics are determined by filter coefficients provided from post-processing circuit 14. Equalizers are well known in the art and may comprise various cascade configurations such as two high pass filters and an all pass filter, two band pass filters and a low pass filter, and various other high, low, or band pass filters at different positions in the cascade. These filters may be analog or digital. When equalizer 10 comprises analog filters, processing circuit 14 alters the filter's time constant to tune the filter transfer characteristic.
FIG. 2A is a typical example of distorted serial data bits that may be received at input 11 of the receiver of FIG. 1A. The channel acts as a low pass filter to selectively attenuate high frequency components of the serial data stream. In general, the distortion is greater for longer cable lengths and higher transmit frequencies. FIG. 2B shows a typical example of the received serial data bits of FIG. 2A after equalization. A goal of channel equalization is to effectively complement the channel transfer characteristic by acting as a high pass filter, so that data bits are properly decoded and bit error rate (BER) is reduced. One of the problems with channel equalization, however, is that all channel characteristics are not the same. Moreover, different cable lengths, data patterns, and frequency significantly affect received power and serial data distortion.
While preceding approaches may provide improvements in high-speed serial data equalization, the present disclosure is directed to further improvements in speed, throughput, and an improved error rate. Accordingly, the preferred implementations described below are directed toward improving upon the prior art.